1. Field of the Invention
This invention relates to a frequency comparator and a PLL (phase locked loop) circuit using the frequency comparator, and more particularly relates to a PLL circuit which synchronizes with NRZ (non return to zero) signal and a frequency comparator which is suitably used for the PLL circuit.
2. Description of Related Art
A conventional PLL circuit which synchronizes with NRZ signal employs a structure which compares the oscillation clock of a voltage control oscillator (VCO) with the outside reference clock frequency which synchronizes with NRZ signal for comparing the frequency. An exemplary circuit of a PLL circuit is shown in FIG. 5.
In FIG. 5, the oscillation clock of a voltage control oscillator 101 is served as one input to a phase comparator (PD) 102 and is served also as one input to a frequency phase comparator (PFD) 104 after the oscillation clock is divided into 1/n (n denotes a natural number) by a frequency divider 103. The phase comparator receives NRZ signal as the other signal, compares the phase of the oscillation clock of the voltage control oscillator 101 with that of the NRZ signal, and generates an UP signal for advancing the phase or a DOWN signal for delaying the phase based on the resultant phase difference.
On the other hand, the frequency phase comparator 104 receives a reference clock which synchronizes with NRZ signal as the other input, compares the 1/n divided oscillation clock of the voltage control oscillator 101 with the frequency of the reference clock, and generates an UP signal for increasing the frequency or a DOWN signal for decreasing the frequency based on the phase difference.
The respective two outputs of the phase comparator 102 and the frequency phase comparator 104 enter to a selector 105. The selector 105 selects one of two comparison outputs of the phase comparator 102 and the frequency phase comparator 104 based on a switching signal given by an external circuit (not shown in the drawing). The comparison output selected by the selector is supplied to the voltage control oscillator 101 through a charge pump circuit 106 and a loop filter 107 as a control voltage.
In the PLL circuit having the structure described herein above, first the selector 105 is switched to the frequency phase comparator 104 side, the frequency that is 1/n clock of the oscillation clock of the voltage control oscillator 101 is drawn to the frequency near to the reference clock based on the comparison output of the frequency phase comparator 104. After drawing, by giving a switching signal from an external circuit to the selector 105, the selector 105 is switched to the phase comparator 102 side. The oscillation clock of the voltage control oscillator 101 is phase-synchronized with NRZ signal based on the comparison output of the phase comparator 102.
The conventional PLL circuit needs a circuit for generating a reference clock which synchronizes with NRZ signal, and also needs an external circuit which detects drawing of 1/n clock frequency of the VCO clock to the frequency near to the reference clock and generates a switching signal to switch the selector 105, and such structure leads to a complex circuit structure. Further, a large loop gain of the phase comparator 102 is needed, and the large loop gain results in poor PLL transfer performance.
A PLL circuit having the structure which compares the phase with only NRZ signal without a reference clock which synchronizes with NRZ signal has been known, which PLL circuit has been developed to solve the problem described herein above. An exemplary circuit of such PLL circuit is shown in FIG. 6. In FIG. 6, an oscillation clock of a voltage control oscillator (VCO) 11 enters to one terminal of a phase comparator (PD) 112 and a frequency comparator (FD) 113 respectively. NRZ signal enters to the other terminal of the phase comparator 112 and frequency comparator 113.
The phase comparator 112 compares the phase of an oscillation clock of the voltage control oscillator 111 and NRZ signal, and generates an UP signal for advancing the phase or a DOWN signal for delaying the phase based on the resultant phase difference. The comparison output of the phase comparator 112 is supplied to the voltage control oscillator 111 through a charge pump circuit 114 and a loop filter 115 as a control voltage for controlling the phase.
On the other hand, the frequency comparator 113 compares an oscillation clock of the voltage control oscillator 111 with a frequency of NRZ signal, and generates an UP signal for increasing the frequency or a DOWN signal for decreasing the frequency based on the resultant frequency difference. The comparison output of the frequency comparator 113 is supplied to the voltage control oscillator 111 through the charge pump circuit 116 and the loop filter 117 as a control voltage for controlling the frequency.
FIG. 7 shows a conventional example of a circuit structure of the frequency comparator 113. NRZ signal, an oscillation clock of the voltage control oscillator 111 shown in FIG. 6, namely VCO clock, CLK, a clock ICLK having the same phase as that of the VCO clock, and a clock QCLK having the phase which delays 90 degrees from that of the clock ICLK are supplied respectively to the conventional circuit.
In FIG. 7, NRZ signal enters to a D-flip-flop (referred to as D-FF hereinafter) 121 as D(data) input and also enters to one terminal of an exclusive-OR (referred to as EX-OR hereinafter) gate 122. D-FF 121 receives a VCO clock as a CK (clock) input. A positive phase output Q of the D-FF 121 enters to the other terminal of the EX-OR gate 122.
The clocks ICLK and QCLK enter to one terminal of respective AND gates 123 and 124. The clock ICLK side input of the AND gate 124 is a negative logic input. The respective outputs of these AND gates 123 and 124 are supplied to D-FF's 125 and 126 as a D-input. The D-FF's 125 and 126 receives an output of the EX-OR gate 122 as a CK input.
Respective positive phase outputs Q of the respective D-FF's 125 and 126 enter to subsequent D-FF 127 and 128 as a D-input, and enter to one terminal of respective AND gates 131 and 132. These D-FF's 127, 128, 129, and 130 receive the VCO clock CLK as the CK input.
Positive phase outputs Q of the D-FF's 129 and 130 enter to the other terminal of the respective AND gates 131 and 132. An output of the AND gate 131 is generated as a DOWN signal for decreasing the frequency and an output of the AND gate 132 is generated as an UP signal for increasing the frequency.
Next, the circuit operation of the frequency comparator having the structure described herein above is described with reference to a timing chart shown in FIG. 8. In the timing chart shown in FIG. 8, an output of the AND gate 124 is denoted by (b), an output of the EX-OR gate 122 is denoted by (c), and the same corresponding components as shown in FIG. 7 are given the same characters shown in FIG. 7.
The output (a) of the AND gate 123 is in "H" level when the clock ICLK and QCLK are both in high level (referred to as "H" level hereinafter), the output (b) of the AND gate 124 is in "H" level when the clock ICLK is in low level (referred to as "L" level hereinafter) and the clock QCLK is in "H" level. The interval while the output (a) of the AND gate 123 is in "H" level is denoted by X, and the interval while the output (b) of the AND gate 124 is in "H" level is denoted by Y.
In a time period of the clock CLK that is the output of the VCO, when a data change of NRZ signal occurs in an interval X as shown in the timing chart in FIG. 8, the data change is detected by the D-FF 121 and the EX-OR gate 122, and the output (c) of the EX-OR gate 122 changes to "H" level.
At that time, because the output (a) of the AND gate 123 is in "H" level, the output (a) is latched by the D-FF 125 at the transition timing of the output (c) of the EX-OR gate 122. The positive phase output Q of the D-FF 125 is thereby changed to "H" level. The positive phase output Q of the D-FF 125 is taken in at the rising timing of the next time period of the VCO clock CLK.
In the next time period of the VCO clock CLK, when the next data change of NRZ signal occurs in an interval Y as shown in the timing chart in FIG. 8, the data change is detected by the D-FF 121 and the EX-OR gate 122, and the output (c) of the EX-OR gate 122 is changed again to "H" level.
At that time, because the output (b) of the AND gate 124 is in "H" level, the output (b) is taken in by the D-FF at the transition timing of the output (c) of the EX-OR gate 122. The positive phase output Q of the D-FF 126 is thereby changed to "H" level. The positive phase output Q of the D-FF 126 is taken in by the D-FF 128 at the rising timing of the next time period of the VCO clock CLK.
The positive phase output Q of the D-FF 127 is also taken in by the D-FF 129. The positive phase outputs Q of the respective D-FF's 128 and 129 are both changed to "H" level, two input of the AND gate 131 are both changed to "H" level, then the output of the AND gate 131 namely UP signal is changed to "H" level.
In other words, when in a time period a data change of NRZ signal occurs in an interval X and in the next time period the next data change of NRZ signal occurs in an interval Y, the time period of VCO clock CLK is shorter than the time period of NRZ signal, that is, the frequency of VCO clock CLK is higher than that of NRZ signal, then a DOWN signal for decreasing the frequency of the VCO clock CLK is generated.
On the other hand, though not shown in the timing chart in FIG. 8, when in a time period a data change of NRZ signal occurs in an interval Y and in the next time period the next data change of NRZ signal occurs in an interval X, because the time period of VCO clock CLK is longer than the time period of NRZ signal, that is, the frequency of the VCO clock CLK is lower than that of NRZ signal, then an UP signal for increasing the frequency of the VCO clock CLK is generated.
However, in such conventional frequency comparator described herein above, because comparison is also performed when the change is not successive as in the case of NRZ data of 10001, the actual phase deviation of only several % is enlarged to the deviation of several ten % due to the space between NRZ data changes, therefore the determination of UP/DOWN could be erroneous. If such erroneous determination continues successively, for example, DOWN signals are generated successively instead of UP signals though UP signals would be generated normally, as the result, the process could be locked just at the double time period of NRZ signal, which locking is sometimes referred to as harmonic lock.
The present invention is accomplished in view of the above-mentioned problem. it is the object of the present invention to provide a frequency comparator which is capable of performing frequency comparison with only NRZ signal without reference clock, and a PLL circuit which will not be involved in the trouble of harmonic lock.